The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory having a precharge circuit for write operation, which is effective to shorten recovery time after writing data to an SRAM and to reduce cycle time.
In an SRAM (Static Random Access Memory), recovery time (time required to make a bit line at a high potential to set a potential difference to zero after write operation) is one of the factors which determines the cycle time. FIG. 2 shows an example of a write circuit and a bit line precharge circuit in a conventional SRAM. Such a conventional technique is disclosed, for example, in "1998 IEEE International Solid-State Circuits Conference, Digest of Technical Papers", pp. 358-359.
In FIG. 2, W1 and W2 denote word lines, and BL1 and BR1 and BL2 and BR2 indicate pairs of bit lines. Memory cells MC1 to MC4 are disposed at intersections of the word lines and the pairs of bit lines. WR1 and WR2 denote write circuits. The write circuit WR1 comprises: an NMOS transistor MNL provided between the bit line BL1 and a power source VSS; an NMOS transistor MNR provided between the bit line BR1 and the power source VSS; NAND gates NW1 and NW2 to which a write control signal WP and data inputs DL1 and DRI are supplied; and inverters IN1 and IN2, which receive outputs of the NAND gates NW1 and NW2. Output signals NL and NR of the inverters IN1 and IN2 are supplied to the gates of the NMOS transistors MNL and MNR, respectively. Although not shown, the write circuit WR2 is constructed in a manner similar to the write circuit WR1.
PR1 and PR2 indicate bit line precharge circuits. The bit line precharge circuit PR1 comprises: a PMOS transistor MP0 provided between the power source VDD and the bit line BL1; a PMOS transistor MP1 provided between the power source VDD and the bit line BR1; and a PMOS transistor MP2 provided between the bit lines BR1 and BL1. A precharge control signal PU is supplied to the gates of the PMOS transistors MP0, MP1 and MP2. Although not shown, the bit line precharge circuit PR2 is constructed in a manner similar to the bit line precharge circuit PR1.
The PMOS transistors will be called precharge PMOS transistors hereinbelow.
FIG. 3 is a diagrammatic sketch of the operations of the conventional technique. The operations of the bit line precharge circuit PR1 and the write circuit WR1, which are connected to the bit lines BL1 and BR1 in the conventional circuit, will be described as an example hereinbelow by using FIGS. 2 and 3.
In a standby mode, all of the word lines, the precharge control signal PU, and the write control signal WP are at a low potential. The precharge PMOS transistors are conductive, the bit lines BL1 and BR1 are at a high potential, and the potential difference (signal amplitude) is zero.
At the time of read operation, first, the precharge control signal PU is set at a high potential and all of the precharge PMOS transistors are made non-conductive. Only one of the word lines corresponding to an address signal is set at a high potential to select a memory cell. In accordance with stored data, a current (cell current) flows to the memory cell from either the bit line BL1 or BR1, so that the potential difference (signal amplitude) occurs between the bit lines. Since the cell current is very small, the signal amplitude of the bit lines at the time of reading operation is small. The signal is generally amplified by a sense amplifier or the like, and the resultant signal is outputted.
At the time of write operation, in a manner similar to the read operation, the precharge control signal PU is set at a high potential to interrupt the precharge PMOS transistors, and only one of the word lines which corresponds to the address signal is set at a high potential. One of the data inputs DL1 or DR1 is at a high potential and the other is at a low potential in accordance with the data to be written. When the write signal WP is set at a high potential, one of the output signals NL or NR of the inverters IN1 and IN2 comes to have a high potential. Consequently, one of the NMOS transistors MNL or MNR is made conductive, and the potential of one of the bit lines BL1 or BR1 is decreased to a low potential, thereby rewriting the data in the memory cell.
After completion of the write and read operations, all of the word lines, write control signal WP, and precharge control signal PU are put back at a low potential, thereby interrupting the memory cell and the write circuit. Further, the precharge PMOS transistors are made conductive, both of the bit lines BL1 and BR1 are precharged to a high potential within a certain time, and the signal amplitude becomes zero (the time required by the operation will be called "recovery time" hereinbelow).
When the read operation is performed after the write operation, the minimum cycle time is determined by the recovery time. In this case, when the cycle time is shortened, at a certain point in time, the read operation of the next cycle starts before the potential difference between the pair of bit lines is reduced to zero. In the read operation, data is read by a signal amplitude of the pair of bit lines. Since the signal amplitude is very small, when the potential difference of the bit lines is not set back to zero at the start of the read operation, data cannot be read normally due to the potential difference. There is the possibility that the access time becomes too long and, in the worst case, data is erroneously read.
As described above, the period since the potential difference between the pair of bit lines is set back to zero in the recovery period after completion of the write operation until the start of read operation of the next cycle in the minimum cycle time. The recovery time is therefore one of the factors which determines the cycle time. For the reduction in cycle time by shortening the recovery time, it is sufficient to increase the size of the precharge PMOS transistor. In this case, however, a load capacity to drive the precharge control signal PUS increases. As a result, delay time caused by making the precharge PMOS transistors non-conductive at the start of read operation increases, and a problem of lengthened access time occurs.